Semiconductor devices are subjected to a series of test procedures in order to assure quality and reliability. This testing procedure conventionally includes "probe testing", in which individual dice, while still on a wafer, are initially tested to determine functionality and speed. Probe cards are used to electrically test die at that level. The electrical connection interfaces with only a single die at a time in wafer; not discrete die.
If the wafer has a yield of functional dice which indicates that quality of the functional dice is likely to be good, each individual die is assembled in a package to form a semiconductor device. Conventionally, the packaging includes a lead frame and a plastic or ceramic housing.
The packaged devices are then subjected to another series of tests, which include burn-in and discrete testing. Discrete testing permits the devices to be tested for speed and for errors which may occur after assembly and after burn-in. Burn-in accelerates failure mechanisms by electrically exercising the devices (UUT) at elevated temperatures, thus eliminating potential failures which would not otherise be apparent at nominal test conditions.
Variations on these procedures permit devices assembled onto circuit arrangements, such as memory boards, to be burned-in, along with the memory board in order to assure reliability of the circuit, as populated with devices. This closed assembly testing assumes that the devices are discretely packaged in order that it can then be performed more readily. It is proposed that devices be packaged without conventional lead frames. This creates two problems for being conventional test methods. Firstly, discrete testing is more difficult because the conventional lead frame package is not used. Furthermore, multiple device may be assembled into a single package, thereby reducing the performance of the package to that of the die with the lowest performance. In other words, the ability to presort the individual dice is limited that obtained through probe testing. Secondly, the packaging may have other limitations which are aggravated by burn-in stress conditions so that the packaging becomes a limitation for burn-in testing.
Semiconductor packaging has been referred to in terms of "levels" of packaging. The chip capsule generally constitutes a first level of packaging. A second level would then be a "card" or a printed circuit board. A third level may include second level packaging combined with a motherboard. A fourth level may follow the third level. In each case, the packaging to a level involves assembly cost.
Ideally, it would be desirable to permit testing of individual dice in a manner similar to that accomplished with discrete packaged semiconductor devices.